[sdiy] modern CEMs?

[ASSI]

On Sonntag, 28. Mai 2006 03:04, wayfar wrote:
> What would be the costs involved, anyone here experienced with asic
> design?

AFAIK the CEM chips were designed on a GEC Plessey analog ASIC process 
which is a predecessor to the ArrayDesign 700 series.  It would be 
interesting to know where Doug Curtis fabs the chips that he's making 
for DSI...

http://www.arraydesign.com/

NRE for the 700 series including a prototype run was quoted to be around 
$10k...$25k with a lead time of one to two months.  Packaged, but 
untested chip in low volume (that is ~10,000 per year) would likely 
cost around $5 per piece.  Test would by far be the highest 
contribution, adding considerable NRE and perhaps $2 or more per chip.

> Would modern fab techniques and materials, lower the cost of making a
> modern version, ex smaller die?

Not really, unless you can take advantage of many more pieces.  The 
actual silicon die is (sometimes much) less than 20% of the cost in low 
volume products.

> Just curious, if theres a fairly steep base manufacturing cost maby
> integrating multiple CEMs with a modern smd package could improve the
> value to cost difference.

You need to keep the power dissipation in check, so this is not a 
panacea.


Achim.
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