[sdiy] New cheap FPGA development system

[Antti Huovilainen]

On Thu, 25 May 2006, Rainer Buchty wrote:

> And with 20 18x18 bit (well, 17x17 bit signed) multipliers you don't
> even have to worry about enough juice for the (formerly) analog
> postprocessing. Although 10 36x36 bit multipliers would be more handy :)

You could use 4 18x18 multipliers to construct one 36x36 multiplier for 
the filter unit. The filter unit could then calculate one sample in 8 
cycles using SSM2044 emulation. Assuming 50 MHz clock rate and 96 kHz 
samplerate, that'd mean 65 voices. Is that enough?-)

Still leaves 16 multipliers for oscillator unit + mixer + VCA.

Antti

"No boom today. Boom tomorrow. There's always a boom tomorrow"
   -- Lt. Cmdr. Ivanova