SV: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!

[René Schmitz]

Magnus Danielson wrote:
> From: René Schmitz <uzs159 at uni-bonn.de>
> Subject: Re: SV: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!
> Date: Wed, 14 Jun 2006 23:55:31 +0200
> Message-ID: <449085D3.4070909 at uni-bonn.de>
> 
>>karl dalen wrote:
>>
>>>--- Magnus Danielson <cfmd at bredband.net> skrev:
>>>
>>>
>>>>So, there is no and will never be any real winner in the Verilog vs. VHDL
>>>>battle. These are the two languagues that has to be supported and one cannot
>>>>make the assumption that one is better than the other.
>>>
>>>
>>>UML.
>>
>>Lisp.
> 
> 
> Look at SDF (Standard Delay Format) and see for yourself. If that won't help,
> just have a look at EDIF. Both highly relevant file-formats and indeed have
> inherit the LISP parantesisomania. On the other hand, from a parser-writes
> perspective it is easy and distinct to parse.
> 
> So no, we have not escaped from LISP.

To me this is no surprise really.

And I wasn't joking... Lisp has the benefit of being easy to parse, and 
while Lisp data and Lisp programs are practically the same thing you can 
pull quite some stunts that are impossible in other languages. IMO 
functional/descriprive programming languages that lend themselves to 
"embedding" other languages (like Lisp, Haskell and so on) are a IMO a 
good candidate for HDLs or descriptive programming in general.

Cheers,
  René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159