[sdiy] Xilinx 3E board comments

[Nicholas Gregorich]

Just thought that I'd add that in the VHDL course I took last year we were still taught to simulate the testbench, then do post synthesis simulations.  We were severely penalized for variation between the pre and post synthesis simulations.  As I remember, its good to get in the habit of inferring flip flops, otherwise the post synthesis simulations would have glitches as logic propagated through various gates and finally showed up at the output ports.

How I wish I could find the time to get back into VHDL.  Obviously I've got to propose a project at work to use them!  ;)

Nick.

On Tuesday, June 13, 2006, at 03:48AM, Magnus Danielson <cfmd at bredband.net> wrote:

--snipped--

>One of the things to learn tought is really the workflow, to design propper
>testbenches, simulate that, then go to synthesis and check the outcome of that
>before hitting the board. Back in the ASIC/full-custom days it was much more
>important than FPGA requires, but it is a good way of doing things never the
>less.
>
>Cheers,
>Magnus
>
>