[sdiy] Xilinx 3E board comments

[Gene Stopp]

Yup like Juergen said, long ago I was doing a lot of VHDL and schematic capture for DIY synth stuff (but it was EPLD, not FPGA, the difference being that you "burn" the EPLD once like a PROM). The company I worked for was closing, and we were transferring the technology to a sister company in Oregon, so I had about six months of lab time and I was doing datacomm EPLD design at the time. So I had the dev system and the blank chips all to myself.

I made a monophonic keyboard interface (which I still have somewhere), a digital pitch-to-voltage converter, a MIDI clock to hardware sync pulse converter, lots of stuff. I did also do an 8-voice keyboard interface, but I never put it in a machine. The ASM-1 was done in that lab too, when we weren't golfing. Cool gig while it lasted :)

And yes, doing the keyboard interface from an existing TTL design (EN #68 I think) brought out the fact that if you're working in a gate array, it's much much faster than lowly TTL or CMOS and you got to get your logic straight or it won't work. You could put a D flip-flop on everything and clock it all from one master clock, or do it right in the first place.

It's funny, the inverse relationship of time and money. Back then I had lots of time and no money, and now I have no time and my FPGA project consists of buying a Nord Modular :) The Xilinx idea seems like a breeding ground for some really complex sound generators and FX stuff. I'm eager to see what's ahead.


- Gene



-----Original Message-----
From: owner-synth-diy at dropmix.xs4all.nl
[mailto:owner-synth-diy at dropmix.xs4all.nl]On Behalf Of James Patchell
Sent: Tuesday, June 13, 2006 3:21 PM
To: Harry Bissell Jr; Magnus Danielson; jhaible at debitel.net
Cc: rainer at buchty.net; synth-diy at dropmix.xs4all.nl
Subject: Re: [sdiy] Xilinx 3E board comments


Good advice...but, if you know how to avoid "hazards" and "races"...it is 
possible...but boy, the tools sure complain about it :-)

At 12:53 PM 6/13/2006 -0700, Harry Bissell Jr wrote:
>Oh yes yes yes... do not EVER try
>an asynchronous design in an FPGA you will
>be SO sorry.   Analog dirty-tricks do not
>work.
>
>H^) harry
>
>--- Magnus Danielson <cfmd at bredband.net> wrote:
>
> > From: jhaible at debitel.net
> > Subject: Re: [sdiy] Xilinx 3E board comments
> > Date: 13 Jun 2006 10:51:06 +0200,Tue, 13 Jun 2006
> > 10:51:06 +0200
> > Message-ID:
> > <1150188666.448e7c7a29f31 at www.debitel.net>
> >
> > > > I'm not familiar with that very Oberheim, but
> > all you will be able to do
> > > > is synthesize the *digital part* of the
> > schematics.
> > >
> > > It is just digital, plus DAC and S&H.
> > >
> > > > And even those
> > > > possibly not 1:1 if they play nasty tricks like
> > prolonguing and
> > > > delaying signals using 7406 and attached R/C
> > where the timing was in a
> > > > way that it matched the specific ratings of the
> > used technology (74,
> > > > 74LS, 74F, ...)
> > >
> > > Oh yes, you're right. Could be replaced with (a
> > lot of) gates and their
> > > propagation delay, or a counter or whatever, but
> > it won't be as straight
> > > forward as it might look at the first glance.
> >
> > If you just put a line of inverters in the VHDL code
> > then the would be
> > (correctly) reduced to a single inverter or no
> > inverter whatsoever. To get them
> > you need to instantiate them explicitly. However,
> > longer delays (many gate-
> > delays) is best nacheived by sampling through DFFs.
> > Then again, this only shows
> > that you approach the problem on a too low level,
> > you try to imitate the low-
> > level details of that implementation. Back up and
> > see what the overall plan is
> > and then re-implement that into a synchronous clock
> > design. Rising edge
> > detection is for instance two DFFs and a LUT (XOR
> > function).
> >
> > At first the tools may be a bit strange, but you
> > learn pretty quickly.
> >
> > Cheers,
> > Magnus
> >

         -Jim
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