SV: [sdiy] Xilinx board as sampler

[synth1 at airmail.net]

>
> But when all this various glue *IP* that has to be added to get something
> to work how much logic is left to do the actuall synthesis part?

The SDD Ram interface is like 1.5% of the *smallest* part :)

> In wich very few actually do decent routing's!

This one is a *timing constraint* driven router (very cool!). You can
specify the end-to-end delay times needed for any net and the router will
place the logic to "beat the clock", so to speak.

The internal gate delay of these parts is measured in *picoseconds*.

Paul S.