[sdiy] Xilinx board as sampler

[synth1 at airmail.net]

a) the board has SDDRam on it, and Xilinx has free IP cores that talk to
it at I think up to 400Mhz speeds. There is also 32MB flash. SDDRam is
dirt-cheap now.

b) there is an Ethernet MAC core for the 3E, but not a PHY. The demo board
uses an external PHY chip (cheap, they are like $3).

c) if you don't want to shell out for the Blaze, just use multiple Picos.
One for the UI, 1 for the sampler, etc. But the Blaze, being 32-bit, is
ideal. Now, if you go to OpenCores website there are also 32-bit
processors there but they are "homebrew" and I have no idea how well they
perform.

d) I would use true audio ADC/DACs on an external daughterboard. The
ADC/DAC on the demo board WILL be good enough to prove out the concept,
but not for final use.

e) yes, there is a "path" for moving FPGAs into 'hard silicon'. But the
minimum order is 5,000pcs if I'm not mistaken. But really: the chip + boot
flash is <$20...big deal. The hard chip would be $5 (no boot needed) but
you need $25K :)

f) the "gate count" of these large FPGAs is more marketing than reality.
There are dedicated "system gates" (mostly clock buffers and I/O pin
drivers) versus "user gates" BUT these "user gates" and clumped into what
Xilinx calls a 'logic block'. The place & route software figures out how
to stick individual gates (like 1 NAND gate on your schematic) into a
logic block (the blocks are like 60 gates pre-wired as a general-purpose
set of logic functions). Logic blocks CAN be shared between different
higher-level functions. Higher-order macos (like a 16-bit up/down counter)
may require 4 "logic blocks" to stick all the gates into. The place &
route tools will tell you the % of the total part used and how many logic
block were required (the PDF files in the previous email show just how BIG
the parts are). Every Xilinx pre-configured part will tell you the # of
blocks needed to implement. Just for fun, you can twiddle the actual gate
placement the software does (it basically is like a pcb autorouter).

Paul S.