[sdiy] Xilinx 3E board comments

[ASSI]

On Freitag, 9. Juni 2006 16:46, Jeff Farr wrote:
> Just looking over the information at xilinx.  What is the difference
> between "System Gates" and "Logic Gates"?

"System Gates" is a meaningless number geared towards folks used to ASIC 
synthesis tools.  In ASIC synthesis the logic density is often 
expressed in "Gates" which is normalized to a 3-input NAND or NOR with 
a fanout of four.  There is even a whitepaper by Xilinx that details 
how their "Sytem Gates" are worth more than Altera's "System 
Gates" (and probably one by Altera claiming the exact opposite).

"Logic Gates" refers to the number of logic blocks the FPGA is made of.  
You will almost never be able to use all of them due to routing 
constraints.

> Are system gates the ones 
> used to "reprogram" the connections between the logic gates?  Also,
> the Ethernet connection is particularly interesting to me but the
> datasheet implies that it is really meant to be used with the
> microblaze, can the pico handle network processing?

The Ethernet IP core from Xilinx is based on the OPB - an extension bus 
for the MicroBlaze - and uses the MicroBlaze for the TCP/IP stack, thus 
only useful with EDK.  If you just need the PHY and can skip the TCP/IP 
stack, you could control the MII interface directly or via picoBlaze.  
Running a TCP/IP stack on the picoBlaze should be possible if you don't 
insist on the full speed of the interface and throw some more (FPGA) 
resources on it like hardware buffering.  It is likely a lot more work 
for you to get things off the ground however, perhaps it might be 
easier to use USB instead.

> multiple FPGA's (Can these things be daisy-chained?)

Yes, this is explained in not much detail in the manual for the DevKit.  
The daisy-chaining is only necessary if you need to have all FPGA 
configured from one source and they all need to come online at the same 
time.

> Ok, one more:  In terms of processing power where do dsp chips fit
> in? Would I be achieving a similar result using a uC and some DSP
> chips, given that I sacrifice a great deal of flexibilty?

An FPGA can run rings around a DSP if you can map the structure of your 
problem to hardware, especially if there is lots of parallelism, many 
different word lengths or plenty of bit-twiddling.  A DSP can't be beat 
for the money and convenience when you really just use a few standard 
word formats with algorithms that map well into (pipelined) loops 
(read: FFT, FIR filters and similar "standard" things).


Achim.
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