SV: Re: [sdiy] Xilinx 3E board comments

[Magnus Danielson]

From: karl dalen <dalenkarl at yahoo.se>
Subject: SV: Re: [sdiy] Xilinx 3E board comments
Date: Wed, 7 Jun 2006 22:28:44 +0200 (CEST)
Message-ID: <20060607202844.22822.qmail at web27609.mail.ukl.yahoo.com>

> >paul wrote:
> >Me, I'm gonna stick 16 32-bit phase accumulators
> >in there with a MicroBlaze uP.
> 
> Oh! He is going to build a rompler! ;-)

Oh, noooo!!! :o)

> >jim wrote:
> >Verilog Rules!
> >:-)
> 
> Is CUPL a dead language?

Pretty much! :o)

> I have a software in wich i can draw everything
> as a basic schematic very easy then compile into
> varius formats or direct to a target device from
> atmel, xlinix, vantis, altera, jedec, palasm, hl
> etc.
> 
> But the software is old so it does not support 
> any new devices! I think its based on CUPL!

GULP!

> PGA!

Hooray!

> Suddenly i felt *very* old! :-(

We have replaced the CUPL vs. PALASM fight with the Verilog vs. VHDL fight.
That is what 20 years does to you.

Yeah, you are getting old. A thad older, grow a big bushy beard (speckled grey
naturally) and you are entiteld to sit on a bench and moan on about anything
and people will just dismiss you as a grumpy old man, AND YOU WILL BE SO PROUD
OF IT! :-D

> Does this mean that analog is out?

Yeah, pretty much. But as a fellow grumpy old man I just ignore facts and fool
around anyway.

Cheers,
Magnus