[sdiy] Single chip digital delay

[Seb Francis]

Antti Huovilainen wrote:

>
> Yes. Cheaper and less trouble than separate ADC & DAC. There is some 
> quality cost but it's unlikely you could get true 100 dB SNR without 
> prior mixed signal experience anyway.
>
This makes a lot of sense.  Previously I had always thought of a CODEC 
in the computer software sense (e.g. mp3 CODEC), but now I  know the 
name in the ADC/DAC sense...

So far I'm looking at Analog Devices, Texas Instruments and Wolfson.  Do 
you know other companies who might make suitable CODEC ICs?

>
> The main issue here is interfacing. You REALLY want constant reliable 
> timing.dsPIC's codec interface would handle that automatically.

I understand .. basically it would be a pain to get the SPI/I2S data 
sent exactly at the right times by the assembly language code in a 
normal PIC, but with a dsPIC you do something like writing the data to a 
buffer area and the hardware clocks it out for you?

>
> That depends on whether it has internal oversampling or not. 
> Preferably you'd want both ADC & DAC to have internal oversampling. 
> Manual oversampling (2-4x) is also possible, but you pretty much need 
> dsPIC or other dsp for that.
>
>
> You downsample the input and upsample the output. In practise this 
> means zero-stuffing and FIR filtering = lots of multiplications = DSP.
> Or you can just get a codec that does it automatically.
>
Ok, I think I'm understanding it now .. the ADC will run at e.g. 768kHz, 
then this will be reduced down to 48kHz by something like averaging.  
Conversely the 48kHz points will be interpolated up to 768kHz for the 
DAC.  I guess this results in more accurate sampling on the way in, and 
on the way out the digital noise frequency will be way higher than audio 
so it will be filtered out more easily and with less distortion of the 
signal from the filters.

I'd imagine it's pretty much a bad idea to try and do this kind of down 
and up sampling in software .. so I am looking for a CODEC chip that 
will do it all for me.

It still might be a 3 chip circuit (apart from any opamp buffers) .. and 
since it's looking like I won't be able to avoid SMD I reckon I might 
make a 4 (rather than 2) channel delay ...

4 in / 4 out CODEC
dsPIC
32kbyte SRAM (should give me up to 85ms per channel and 16bit/48kHz)

Thanks for your help,
Seb