[sdiy] MOSFET ANGST

[Magnus Danielson]

From: Scott Gravenhorst <music.maker at gte.net>
Subject: [sdiy] MOSFET ANGST
Date: Sat, 17 Jul 2004 17:19:08 -0700
Message-ID: <200407180019.i6I0J7Z27411 at linux6.lan>

Scott,

> I have started doing a few experiments, simple stuff just to see if what is
> supposed to happen actually does.  So I built a little voltage controlled
> attenuator.  It sort of works...  read on.
> 
> Please see http://home1.gte.net/res0658s/MOSFET_test.gif

Here I instantly spot that you lack the linearizing resistor setup. Read on and
you know why...

> In all cases, the AC input is a triangle waveform from a signal generator.
> 
> I started with "A" and noted what I would call unkindly behavior.  At zero
> gate volts, the output is "full scale" and looks like a proper triangle
> waveform.  However, as I increased the gate voltage, generally, the
> amplitude of the output was attenuated as expected, but there is
> assymetrical distortion.  I looks like as the gate voltage increases, the
> negative portion starts to soft clip _first_, then after the voltage
> increases more, the positive portion begins to drop in amplitude, but no
> soft clipping occurs!
> 
> Ok, so I thought perhaps I needed to do experiment "B", which uses both the
> P and the N transistors.  Guess what...  No difference, meaning that as the
> gate voltage increases, there is attenuation, but the signal is still
> asymmetrically distorted.  I also tried reversing the drain and source
> connections of the P transistor - no difference.
> 
> WARNING: THIS MAY PROBABLY BE POORLY WORDED, NON-EE LANGUAGE.
> I got suspicious that the P transistor wasn't doing anything because it
> appears to me to be reverse biased, i.e., in normal inverter use, it's
> source is more positive than it's drain and the more negative the gate is
> with respect to it's source, the less it conducts.  It looks like both the
> N and P MOSFETs are depletion mode, (I can't find this in the datasheet)
> but the fact that they are opposite types (N vs P) means they work opposite
> and make a nice inverter with 2 transistors.
> 
> Anyway, I did experiment "C" and found no change in output at all as gate
> voltage increases.  As in nothing happens when I turn the knob.  To my way
> of seeing it, this means that the idea of folding a 4069UB (i.e.,
> connecting pin 14 to pin 7) has no advantage because the P transistors
> won't do anything for us.
> 
> I'm looking for pointers, explanations, etc., like "HEY SCOTT, YOU
> BONEHEAD, YOU NEED TO CONNECT THE FRAMUS TO THE PHLORBIS THROUGH A
> HYPERSPACE MULTIZORCH!".

First of all, your conclusion about the MOSFETs are correct, you need an
inverted instance of the control-voltage to drive the P-MOSFET as compared to
the N-MOSFET. Such an inverted signal is quickly done with a spare 4069UB
inverter and a pair of resistors, which you would find me indicating in my
initial responce to your schematic post.

> Is this kind of asymmetrical distortion expected?

Yes.

If you read the fine-print you will find that the MOSFET is sensitive to both
the drain-source voltage and the gate voltage. This is really where the
linearizing diodes come in. They don't really linearize things but rather 
create a nice 1:1 mix of the voltages such that the drain-source voltage
dependence cancels out (in the first degree at least).

> If not, how the héll do I fix it?  I thought that using such a low input
> would be wonderful...  Ok, I tried reducing the input voltage to
> 40 millivolts, it looks better, but still asymmetrical.

This is in perfect correlation with what is to be expected from theory! 

> Help???

Linearizing resistors! You already know how they are wired, so you just need to
include them in your test-setup and fire away!

I'd love to hear how hard you can drive them without excess distorsion!

Cheers,
Magnus