[sdiy] website update - VC-Delay

Fri Jul 16 00:00:07 CEST 2004

Scott Stites <scottnoanh at peoplepc.com> wrote:
>Hmmm....
>
>I'd sure like to see the trick of RAM addressing applied 
>successfully to the PT2395 - I, too, would like to see the device 
>provide very short delays (which interest me more than the longer 
>delays also). 
>
>As for using two delay devices, a couple of years ago I tried 
>this with the PT2395's little brother, the PT2399. On the spec 
>sheet, it's capable of a delay of 31.3 ms. Seems to me I was able 
>to push it to as little as 17 ms, though I could be wrong about 
>that (a bit hard to measure on the equipment I have available). 
>
>It's a fairly touchy area of adjustment, but I was able to get 
>comb filter type effects using the technique. Not as 'smooth' as 
>one would get from a BBD, but interesting nonetheless, and could 
>probably be improved knowing now what I didn't know then. At the 
>absolute minimum delay, I don't recall there being perceivable 
>latency when listening to the purely wet signal. 
>
>The main drawback of the PT2399 is that you do not have an input 
>for an external clock - the internal clock frequency is 
>controlled by the resistance of a pin to ground. I've used 
>LED/LDR's (such as used by Scott Bernardi), current sinks (though 
>not explored thoroughly) 

If this IC is using the resistor to ground as a "current sink", then 
it seems that an opamp with BE junction of a darlington pair inside
the feedback loop with collector to the pin instead of the resistor
might work.  + input to ground.  You have to make sure you have the 
correct transistor type (NPN vs PNP) so that conduction is in the 
correct direction.  Then feeding the summing node with a current will 
cause the collector emitter circuit to have an inverse copy of that 
current.  Essentially, the collector emitter circuit becomes the 
resistor which goes to the opamp's summing node virual ground.  This
will give nice linear control over the current.  Something to try if 
you have not.

>and FET's. I actually have gotten the 
>widest range of use using a FET, though there are inherent 
>linearity issues there. Perhaps expo control of a FET's 
>resistance would work really well for 'flange' type comb filter 
>effects. Obviously, one still needs linear control for chorusing. 
>In any event, a chorused 'echo' is quite easy to accomplish with 
>the PT2399 without going through a lot of histrionics. 
>
>Of course, with the PT2395, one could try hopping up the clock to 
>around 44 MHz or so - that would probably do the trick ;-). 
>
>If all else fails, look to Rene Schmitz's digital delay. But, 
>bang away at the PT2395 - I'd *love* it if someone cracked the 
>problem. 
>
>Cheers,
>Scott
>
>
>
>-----Original Message-----
>From: Theo <t.hogers at home.nl>
>Sent: Jul 15, 2004 3:45 PM
>To: destrukto at cox.net, synth-diy at dropmix.xs4all.nl
>Subject: Re: [sdiy] website update - VC-Delay
>
>The RAM addressing is probably straight forward.
>If I had to do it I would first read the delay-ed data and than write the
>new "sample" to the same address.
>However the CAS/RAS multiplexing is why lifting address lines don't work,
>even in the simple scenario above.
>They may write both CAS and RAS for every access or use burst mode and only
>write CAS on a new cycle of the RAS counter.
>Monitoring the CAS line with a scope would tell you.
>
>Anyways, to drop address lines you (probably) need to do so for CAS only.
>Some gates that block part of the CAS data might work.
>That would need 2 or 3 standard TTL ICs.
>
>Also completely other variation comes to mind.
>Use two delay ICs, one with a fixed delay the other with VC.
>That would result in a direct signal with a delayed chorus, could be a nice
>effect in it self.
>Using some smart audio routing the same unit also may do more complicated
>delay work.
>
>When doing the above, the shortest delay of the chorus would be around 33ms.
>Don't know if 33ms or so "latency" of the chorus would be a problem.
>Walking on thin ice here, but cause the "latency" is under the 50ms,
>chorus and direct signal may be perceived as one.
>
>Just me 2 cnt.
>
>Theo
>
>
>
>
>----- Original Message -----
>From: Ryan Williams <destrukto at cox.net>
>To: <synth-diy at dropmix.xs4all.nl>
>Sent: Thursday, July 15, 2004 7:00 PM
>Subject: Re: [sdiy] website update - VC-Delay
>
>
>>
>>
>> I originally planned on doing another chorus type circuit using a few of
>> these but couldn't figure out how to shorten the RAM size. It was
>> suggested that it could be done by simply disconnecting address lines. I
>> tried that and couldn't get it to work and left it at that because I
>> wanted to finish my module and move on to something different. If anyone
>> figures that out, I would like to hear about it.
>>
>> but, I had another idea that might work out. that is to put a similar
>> circuit in a FGPA. it's more expensive and alot more work but I plan on
>> trying this after I finish my digital IC design course and also finish
>> some other projects and save enough money for a development board (that
>> might be a while). I suppose it would be easier to find out what the RAM
>> access pattern of that PT2395 is.
>>
>> -ryan
>>
>> Nils Pipenbrinck wrote:
>>
>> > Ryan's circuit made me think.... I doubt that the delay chip does any
>> > complicated acesses to the ram: Most probably it just alternates between
>> > write a byte and read a byte.. maybe even with a fixed address offset or
>> > no offset at all.
>> >
>> > If we would ignore the internal address-logic of the chip and roll our
>> > own we could make the delay time as small as we would like to, right?
>> > Can't be that complicated. I doubt we'll need much more than some
>> > counters and a binary adder.
>> >
>> > So, does anyone knows the ram access pattern of the PT2395?
>> >  Nils
>>
>>
>>
>
>
>
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