[sdiy] Quad linear AD

[fmg]

Basically this circuit is a transistor constant current source-current
sink.

Below is a composed image of Electronics Workbench screenshots.

http://www.geocities.com/eqys/var_tmp/lin_AD_dis_x4_pre.gif

The discrete input buffer could be replaced for a CMOS buffer
(a pair of inverters, i.e.) to make it simpler.

The "x3" point is for the other output stages.

P1 is a combination of a 100k log pot (or 50k or 20k for shorter
attacks) in serie with 100ohms resistor (shown fully closed in the .gif)
Similar, P2 is a 100k log pot (or 500k for long decays) in serie with
100ohms resistor (shown fully open).

The oscope shows a range of ~17ms...4.5s. A wider range is posible with
1M pots and a .47uF capacitor, but the "taper" of log pots is an issue
here. A cubic response could turn them more usables.

The output is unbuffered. Any jfet opamp capable of move its output
near to rails *should* work. The ca3130 is an ideal candidate for
circuits that must remain single supply.

I hear for suggestions, corrections, etc.


Fabio Gonzalez