[sdiy] Taking a Step towards - - --((FUTURE-PREDICTIONS))-- - -

[Richard Wentk]

At 12:15 12/01/2004 +0100, Karl Dalen wrote:
>As a suprising thing that the academics did discover some time
>ago are that even such simple thing as a e.g elctric string bass
>would easily require as much as 3900 to 4000 partials to be
>resynthesised well. Bass notes how strange it may "sound"
>requires an a massive amount of partials!

If the partials are harmonic - which mostly they are - that would mean a 
20Hz bass note would have partials spreading up to about 80k. I think 
you'll find we can lose about three quarters of those. ;)

Anyway - I wouldn't be interested in recreating sampling. 256 partials is 
just fine for a lot of sounds, if you use them non-contiguously. In my 
experience with resynthesis, 1024 contiguous partials would cover most 
applications.

There's an additional benefit, because severe band-limiting - as in brick 
wall filtering - seems to sound warm. I have no idea why, but it does.

>Besides there is much different aproach in additive besides the
>old oscillator bank idea, check out some of Xavier Rodhets
>research. As a speculation his invert FFT might be used in
>the Neuron.

I/FFTs have issues with timbral granularity. You're effectively limited to 
resynthesising sounds which last a certain minimum duration. You can 
improve on this by using windows and overlaps, but at the cost of a lot of 
extra processing.

Oscillator-based resynthesis doesn't have these problems. The down-side is 
you (optionally) need some form of partial tracking to prevent big skips, 
which would add transients.

>If one would implement a oscillator bank in a FPGA should check
>out the bell labs papers of the "intelligent oscillator" used
>in the Synergy" It could be a nice staring point i suppose!?
>They uses phase information to set amplitudes instead of
>multiply, if im not remembering completely wrong!

That's one approach, but with so many multipliers on a chip I'm not sure it 
would any more efficient than just doing it the brute force way for an FPGA 
implementation.

Richard