[sdiy] Re: Cauer Filter Design

[Magnus Danielson]

From: Ian Fritz <ijfritz at earthlink.net>
Subject: Re: [sdiy] Re: Cauer Filter Design
Date: Tue, 06 Jan 2004 10:28:32 -0700
Message-ID: <5.1.0.14.2.20040106101955.00ab4ea8 at 127.0.0.1>

> Hi Mangus!
> 
>    :-)

Hi Nai!

>:)

> At 01:35 AM 1/6/2004, Magnus Danielson wrote:
> 
> >As a side-note, as I looked through the SSM 2040 datasheet earlier I saw a
> >4-pole Cauer setup. It's in Figure 8 on page 3 of the 4-page datasheet that I
> >have. You could naturally make a 10th order variant if you really wish.
> 
> 
> Did you ever check the math on that datasheet?

Nope. I was checking the SSM and CEM datasheets for patent numbers in a patent
survey. I also think I resolved a few "patent pending" into the now published
patent numbers. So, as you can imagine, checking the math on them where not
really on my list of things to do. Maybe I should do that one day when I'm
bore.. Bhahahahahaaaa! Ehum.. well, so when I was looking through those
datasheets I just saw it in the passing and made a mental note of it. More to
show that there might be fairly compact implementations than anything else.

> At one point, I convinced myself that some of it is incorrect.
> 
> The source of the error seemed to be the same one that Bernie Hutchins and 
> I discovered just  a couple of years ago in an old Electronotes circuit.
> 
> That circuit was a voltage-controlled Butterworth design from S. Franco.  I 
> built it (was I really the first one ever??) and found a pronounced 
> peaking.  I asked Bernie if there was an error on the schematic, and he 
> figured out that the error apparently came from assuming that one of the 
> OTAs behaved like a current-controlled resistor (CCR).  This behavior only 
> holds when the OTA output is at zero potential, e.g., when driving an op 
> amp summing node.  Otherwise you have to be careful to solve the correct 
> node equations using the OTA transconductance expression.

Interesting. Well, that does it then, from now on I should check the math on
these things. Even if I make errors myself (I did a tiny little slipup on my
SVF calculus, but really tiny... you can be led to beleive that I had
normalized the frequency, which I haven't, so if you just handle that it should
be OK).

Ain, Thanks for the comment on that!

Hmm... now, maybe one SHOULD check the formulas of popular VCF chips and see
which ones are wrong, and then check on various implementations and see if the
error made it into production units. That might be interesting and some
character differences for you...

The Cauer responce may not be the most popular, but the Butterworth or
Synchronous I expect.

Cheers,
Magnus