[sdiy] Varying gate lengths (using a 4017 counter) for a simple sequencer?

[fmg]

Harry,

I'm not familiar with the technique you are describing (wishing to know
more about it). Is that a sort of periodic charge pumping? Something that
alters the normal charge curve of a capacitor in a staircased shape?
In that manner the comparators could be locked at any selectable fraction
of time (given by the external clock period)
Oops...sorry my "technical" language... I just tried to figure out how
it could work.

Anyhow I'm very busy with my job now, this "frozen" project will be so
for some time (at least for this year).

Side Note: early this year I bought 4000 NPNs and 2700 PNPs transistors,
and recently, fall in my hands an old mag (1971) describing discrete
flip-flops and ring counters.  Wouldn't this be a Signal?

(As soon as possible I'll buy more trannies just in case another IC (like
4017) or PNPs (or even NPNs) were to be discountinued.)

Best regards,

Fabio
.

harrybissell wrote:
> 
> Have you given any thought to adding a clock that produces very narrow pulses...
> then imposing these on the capacitors for each stage ?   This is a method that was
> used
> for syncronizing timers in the days before digital counters...   This would allow
> you to get
> times that are multiples of the clock... so each stage could be one, two three...
> n pulses long.
> 
> If you use the clock, the outputs WOULD be rhythmic but still have variable times.
> Turn off the
> sync pulses, and your original circuit is back...
> 
> I like your self-clocked idea. Cool!
> 
> H^) harry
>