[sdiy] Maxim analog switch ICs

[Grant Richter]

> The key idea is that the input voltage is first converted into a
> current, and then converted back into a voltage. So the switch never
> sees a voltage greater than a couple of millivolts, if its on, and less
> than +-0.6V when its off. Thus a lowly 4000 series switch can handle
> 15Vpp signals. Its much like the corresponding jFET circuits.

Using the 4000 series CMOS in the current mode into a summing node has a
couple of drawbacks.

Off isolation is compromised as leakage currents are larger than the
resistive (voltage mode) isolation. A 15 volt signal is only attenuated to
about 1 volt.

The switching of the summing node can cause signals to be sent back up the
inputs as voltage at the summing node moves up and down from leakage
currents or something.

You may need to bias the ground pin to -0.7 volts to correctly handle a -15
volt input.

Not all 4000s are the same. The ST HCF4066 series will allow this, but not
the Fairchild CD4066 (blows up).