[sdiy] simple TTL programmable counter question (74LS163)

[Colin Hinz]

On Mon, 27 Oct 2003, Ken Stone wrote:

>
> >> You can see what I was doing in a similar project here. Admittedly I haven't
> >> tested this PCB, but my prototype certainly ran fine. I think I also did one
> >> using the 161, but I forget!
> >>
> >> http://www.cgs.synth.net/modules/cgs20_dco.html
> >
> >No, you where using 193 and not either of 161 or 163s.
>
> ALSO did one with 161 or 163. The count direction is reversed (i.e. an up
> count, so it was pain, and I went back to the 193.

The trouble with using '193 counters is that the counter re-load is
asynchronous, which means that instead of getting a precise "divide
by N" you get a "divide by [ N + Y ], where Y is the total propagation
time for the carry to cascade through all the counter chips and
through the one-shot (if present). If your load pulse is timed such
that it lands within the actual setup/hold window of the input
clock, you could find that Y will vary between cycles. You're
certainly going to get some jitter caused by variations of when the
load pulse takes effect, within a cycle. Scary! You sure you want this?

> >> Not with LS TTL! they flake at about 25 MHz.
> >
> > I agree, for those speeds I would use a small CPLD or FPGA today.
> > Cheap and fairly easy to get the intended performance.
>
> The HC, ACT, and HCT series can get better frequencies, but I
> don't recall how much better.

According to TI's website, HC/HCT are in general actually slower
than LS-TTL, though not significantly so. You won't find a '193
from a fast logic family, though, as the ripple-carry clock
operation is incompatible with fast clock speeds. F-TTL is
going to be as fast as it's going to get. Even so, the four
stages (for a 16-bit counter) of clock-to-carry delay means
that at maximum clock speeds, you're going to be reloading
the counter a few clocks later than you ought to be.

See why I like nice, all-synchronous designs? If you want to
stick to discrete TTL chips, get to know well the 74LS163,
as it will make a good friend.

And yeah, programmable logic is the "sensible" way to do it
these days. About 6 lines of VHDL and you're done....and the
PLD will certainly be cheaper than a bunch of discrete TTL.
But yeah, it's less fun when hardware turns into a glorified
programming exercise :=)

- Colin Hinz
  Toronto, Canada
  digital design weenie