[sdiy] Latch-up question

[fmg]

Hi all

I'm working in an adsr-r/env_gen and am facing the posibility
of phase-reversal issue in one (or two) of TL08x I included
in the design.

What follows is an excerpt of National's AN447:

>"In open-loop operation (i.e., no feedback from output to in-
>verting input, or, during any time that the opamp is slew-rate
>limited), taking the non-inverting input below the inverting
>input causes the output to slew toward the negative supply
>rail. If the voltage at the non-inverting input is more negative
>than the negative common-mode limit, the input stage ceas-
>es to function properly and the output swings to its positive
>limit. This apparent ``phase-reversal'' is temporary; bringing
>the non-inverting input back within the legal input common-
>mode range restores the part's normal operation."

Now, wich is the "negative common-mode limit" ?

In the TL081 datasheet is spec'ed:

>Differential Input Voltage +/-30V
>
>Parameter           Condition       Min        Typ
>------------------------------------------------------------
>Input Common-Mode       Vs +/-15V     +/-11V    +15V/-12V
>Voltage Range

Should I consider -11V the limit for the non-inverting input to
be in a safe area from latch-up?

...even if the inverting input is at a diode below Vdd (+14.4V) ?

Are these assumptions wrong?


I'll appreciate any comments about.

Thanks,

Fabio Gonzalez