Re: Re: [sdiy] Parallel processing clock design question

[Roman]

let's try not to kill ourselves over one or two
micro's cycles. Cant say about AVR, but in PIC
it would look like:

using interrupt:

main_loop:
     goto main_loop
interrupt:
     call minimoog_vcf   ;whatever instruction of interest
     .
     .
     .
     bcf INTF        ;clear interrupt flag
     retfie

using polling:

main_loop:
     btfss SAMPLEin
     goto main_loop
     call minimoog_vcf
     .
     .
     .
wait_until_clock_low:
     btfsc SAMPLEin
     goto wait_until_clock_low
     goto main_loop

so actually, polling requires one more instruction to enter than interrupting. We don't need to save anything after interrupt, so it doesn't require any overhead. And when returning to the main loop we must make sure that sample clock is already LOW, otherwise it'd enter the loop again within same sample time.

Roman

---- Wiadomość Oryginalna ----
Od: René Schmitz <uzs159 at uni-bonn.de>
Do: jbv <jbv.silences at club-internet.fr>
Kopia do: Magnus Danielson <cfmd at swipnet.se>,synth-diy at dropmix.xs4all.nl
Data: Tue, 15 Jul 2003 17:30:50 +0200
Temat: Re: [sdiy] Parallel processing clock design question

<snip>

>Here polling your syncing signal has a distinct advantage of shorter and 
>consistent response time. And if you're going to "burn off" the unneeded 
>performance anyway, you don't loose anything.
>
>
>Cheers,
>  René
>
>-- 
>uzs159 at uni-bonn.de
>http://www.uni-bonn.de/~uzs159
>
>
>
>