Re: Re: [sdiy] Parallel processing clock design question

[Roman]

Od: Magnus Danielson <cfmd at swipnet.se>

>NO! NO! NO!
>
>48 kHz is a high interrupt frequency. Using interrupt for syncing at that
>rate is a BAD idea. Even 8 kHz is considered high on many micros. 

It's for audio use in 48kHz sampled system, so whatever micro is doing, it has to fit within 1/48ksps = 20.83us. They need the 48kHz anyhow, to at least spit the result at desired rate. For fast AVR that could be hundreds of instructions per sample (coorect me if I'm wrong, I'm no AVR user), fair enough for some signal processing.

>No, using a single crystal oscillator and then use a buffer to distribute to
>the CPUs is a good solution which works well. Doing it this way allows both

if done properly, yes. And I could see the need for syncing also reset of all 5 micros. One fast rising edge brings all micros from reset at once, and they're synced then.

>If synchronisation between the CPUs is needed, distribute a sample-rate clock
>as well, and then put a while-loop in all CPUs code. Each CPU must work faster
>than the sample time anyway, and the residue cycles is wasted. A while-loop
>that loops until the sample-rate clock goes high will actually work well with
>even more advanced machines. Simple and effective. No strange things happening
>eating cycles unexpectively.

well, that's basically what I've proposed. It doesn't really matter if the micro polls external sample clock, or waits for interrupt from it.

Roman