[sdiy] Parallel processing clock design question

[Bert Schiettecatte]

> jbv wrote:
> > I agree that this is some kind of brute force method, and may be
> > not the most elegant design, but it might work quite well.
> > The advantage of this method is that, when interrupt starts, there's
no
> > need to save registers and such, since the main task is doing
nothing.
> > Furthermore, the uC I'm planing to use (the Scenix SX) has a very
> > short interrupt rersponse time (50 to 60 ns IIRC).

Before anyone gets into building a design with the Scenix SX family:
they are the biggest joke in microcontroller history. No decent C
compiler available, and a nightmare to program in assembly. Quite
expensive too for what they are. I would stay away from them and use
Atmel AVR or something else. 

Bert (who totally hates Scenix now after wasting several weeks on it in
the summer of 2001)

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