[sdiy] Parallel processing clock design question

[Tom Arnold]

On Tue, Jul 15, 2003 at 02:47:04PM +0100, jbv wrote:
> I agree that this is some kind of brute force method, and may be
> not the most elegant design, but it might work quite well.
> The advantage of this method is that, when interrupt starts, there's no
> need to save registers and such, since the main task is doing nothing.
> Furthermore, the uC I'm planing to use (the Scenix SX) has a very
> short interrupt rersponse time (50 to 60 ns IIRC).

I use this exact method with this chip also.  I'm using the SX52 clocked
at 50mhz.  My code loop knows how to throw its samples around when it gets
an interupt and thats it.  Why code it this way?  Was the most simular
method to how the circuit I am cloning originally worked.
( Electroharmonix 16second delay )

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