[sdiy] Parallel processing clock design question

[Magnus Danielson]

From: Roman <modular at go2.pl>
Subject: Re: [sdiy] Parallel processing clock design question
Date: Mon, 14 Jul 2003 11:26:10 +0100

> if it's for sound synthesis, why not use separate
> XTALs and sync the micros using interrupt at sample
> rate. If all communication between them happens
> just after interrupt, they will be synced exactly
> on instruction. Even without that in mind, at 48ksps,
> micros can desync (is that a word?) no more than
> 1 clock cycle at 0.1% initial frequency accuracy.
> Common XTALs are better than that AFAIK.
> 
> And having only 48kHz signal on whole PCB is much
> easier to handle than 1000 times higher frequency.

NO! NO! NO!

48 kHz is a high interrupt frequency. Using interrupt for syncing at that
rate is a BAD idea. Even 8 kHz is considered high on many micros. The more
advanced machines, the more crap happends on interrupt before the first
instruction is executed, and the more stuff you have to do to keep things
clean.

No, using a single crystal oscillator and then use a buffer to distribute to
the CPUs is a good solution which works well. Doing it this way allows both
for open-end impedance-missmatch and propper matching for the frequency which
was discussed. It should work fairly well even if not using high quality
clock buffers.

If synchronisation between the CPUs is needed, distribute a sample-rate clock
as well, and then put a while-loop in all CPUs code. Each CPU must work faster
than the sample time anyway, and the residue cycles is wasted. A while-loop
that loops until the sample-rate clock goes high will actually work well with
even more advanced machines. Simple and effective. No strange things happening
eating cycles unexpectively.

Naturally should the sample-rate and CPU clocks be synchronous.

Cheers,
Magnus