[sdiy] Parallel processing clock design question

[Ingo Debus]

jbv wrote:
> Let's say I want several (2 to 5) uCs to run in
> parallel (yes, this is related to the recent thread
> "sound synthesis with uC") at high speed (40 /
> 50 MHz or more).
> 
> What is the best solution for clock design :
> 
> 1) use only 1 Xtal, which means rather long
> connections between Xtal and each uC clk
> input
> 
> 2) use 1 Xtal per uC, which means more parts
> and more PCB room but smaller connections
> 
> 3) use only 1 Xtal, but at lower freq and hook
> each uC clk input with a freq multiplier
> 
> 4) use another smarter solution that hasn't
> crossed my mind yet but that will be submited
> by some smart list member any time soon...

Opposed to others who answered, I vote for option (1). Quartzes are so 
cheap nowadays, and it's really easy to mess up a clock signal in the 
tens of MHz range, when PCB layout isn't done carefully. Perhaps two 
to five quartzes are even cheaper than an oscillator with a proper 
clock drive circuit.

Ingo