[sdiy] Parallel processing clock design question

[The Proteus]

jbv,

     I'd use a combination of method 1 and 4, preferrably. A former
employer of mine used a clock routed into a fast octal buffer, then
dedicated individual outputs of the buffer to the ASICs we had on
board. This gave us two advantages. First, since you have each clock
coming from a single buffer, you don't have to worry about
overloading your clock net. Second, it makes control of trace
impedance and (if needed) transmission line characteristics easier.
In prototyping, we'd place zero ohm resistors at each end of the
trace to tune the clock nets, and to verify our calculations in both
SPECCTRAQuest and SPICE for the transmission line analysis. Granted,
this was for a total of 7 ICs, and the clock frequency was in the
25MHz range... nothing too fancy.

Regards,

Joe

jbv said:
> Hi again,
>
> Let's say I want several (2 to 5) uCs to run in
> parallel (yes, this is related to the recent thread
> "sound synthesis with uC") at high speed (40 /
> 50 MHz or more).
>
> What is the best solution for clock design :
>
> 1) use only 1 Xtal, which means rather long
> connections between Xtal and each uC clk
> input
>
> 2) use 1 Xtal per uC, which means more parts
> and more PCB room but smaller connections
>
> 3) use only 1 Xtal, but at lower freq and hook
> each uC clk input with a freq multiplier
>
> 4) use another smarter solution that hasn't
> crossed my mind yet but that will be submited
> by some smart list member any time soon...
>
> Thanks in advance,
> JB
>
>
>