[sdiy] Parallel processing clock design question

[James Patchell]

         It is best to use a clock source, such as a oscillator, that can 
drive into the characteristic impeadence of the traces on your PC 
board.  You then route the clock as a single continuous line, preferably 
not through any vias with a terminator on the end.  I have found this 
methode a pretty good one for routing clocks.  I used this in a system I 
did that had 12,000 uP chips in it running in parrallel.

         -Jim


At 10:32 PM 7/12/2003 +0100, jbv wrote:
>Hi again,
>
>Let's say I want several (2 to 5) uCs to run in
>parallel (yes, this is related to the recent thread
>"sound synthesis with uC") at high speed (40 /
>50 MHz or more).
>
>What is the best solution for clock design :
>
>1) use only 1 Xtal, which means rather long
>connections between Xtal and each uC clk
>input
>
>2) use 1 Xtal per uC, which means more parts
>and more PCB room but smaller connections
>
>3) use only 1 Xtal, but at lower freq and hook
>each uC clk input with a freq multiplier
>
>4) use another smarter solution that hasn't
>crossed my mind yet but that will be submited
>by some smart list member any time soon...
>
>Thanks in advance,
>JB