[sdiy] very simple vco

[René Schmitz]

Hi Scott,

Scott Gravenhorst wrote:

> Ok, 2 parts I don't understand here: temperature problems with this particular
> CCO and temperature problems with a linear current source.  

Any CCO ultimately depends on the accuracy of the components involved. 
(Like everything...) Tempcos of the resistors, caps, drift of opamps, 
transistors and so on.

I recommend to read the excellent articles from Ian Fritz about his 
VCOs, he goes into great length describing how he compensated the drift 
of his CCOs. Also we had quite some debate here about "tune drift". (As 
opposed to the expos "scale drift".)

> It was my understanding that the linear current source is accurate because the
> summing node causes copying of the input current by ensuring the node remains at
> zero volts through the opamp output doing whatever is necessary to make that
> happen.  I can't see how temperature effects or even nonlinearities in the
> feedback loop would upset this.  Obviously I am missing something.  Whatever
> temperature effects there are, I would guess they are minor since my linear VCOs
> seem to stay in tune.

Your analysis of the circuit is based on the assumption that there is no 
current through the base of the darlington. In reality there is. That 
means you have to supply Ic+Ib at the summing node, because Ie = Ic+Ib.
But the CCO will only see Ic. Especially at low currents beta will go 
down, and the effect could be more noticeable. And beta depends on 
temperature....

Another matter are the opamp drifts. The offset voltage drift of your 
input opamp directly translates to a shift in frequency for example.

But as you say, the effects are probably minor.

I'm just thinking we have analysed the expo current sink to great 
lengths, and I think only few cared to make a similar analysis on the 
linear sources.

> As for this particular 4069 CCO, what is it about it that makes it "unstable"? 
> What causes the drift?  Is this a CMOS temperature thing?  As you say, it
> doesn't seem all that bad.

I think the dominant error will be the capacitor tempco. The circuit is 
almost "ovenized" so thermal effects of the CMOS transistors are 
probably not an issue. I think the values of the resistors for the 
hysteresis should track pretty well. (Assuming similar tempcos for both.)

Cheers,
  René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159