[sdiy] S&H

[Paul Maddox]

Richard,

> I'd doubt this. You'd be building something which leaves a negative amount
> of room for component tolerances. That's not usually a good idea.

This is why Im not keen on doing it.

> Why not buffer the incoming data with its own independent (dual-port?)
> memory, so you can stretch out the 32 channel update cycle over the whole
> of the 10us? It would be a bit of a pain to design but at least you'd be
in
> digital land where things mostly have hard edges, and not trying to deal
> with the problem in a fuzzy analogue way.

Yeah, I've been thinking about this but there are two problems..
1) dual port memory is *VEY* expensive, 64Kbyte will cost about £40.
2) To do it in an FPGA would mean an insane amount of IO and one DAC per
oscillator.

> I don't know how you're driving the S&Hs or what you're driving them with,
> but this might make the specifications for your software more relaxed too.

I was trying to use ONE DAC to generate 32 oscillators (for a polysynth),
but it looks like I wont be able to do it.
so I'll try and find some quad/octal DACs that I can use instead, its a
shame, but its probably a better soloution than the singleDac+S&H method, it
just takes more board space...

Paul