[sdiy] RAS/CAS timing

[Rainer Buchty]

> I'm asking this cause I never built a board involving RAMs and, as I
> see in datasheets, don't want to ruin my life trying to design
> RAS/CAS/WE/Mux timings. (well, it's already ruined but don't want go
> further...)

With that old stuff timing is pretty simple, basically an 8-state machine
does the job:

(1)	apply row address
(2)	lower RAS#
(3)	apply col address	and	apply data (write only)
(4)	lower CAS#
(5)	set R/W# line
(6)				and	fetch data (read only)
(7)	raise R/W#
(8)	raise RAS#/CAS#

Now that we have DRAM you need to periodically refresh the content which
can be done in many ways:

(1) If you cyclically read all the contents within the desired time, no
separate refresh is needed.

(2) Otherwise you need to refresh, where you have a choice of flavors
depending on the chip. As you probably want to fit that into the already
existing state machine this should work:

- RAS-only refresh
(1)	apply refresh row address
(2)	lower RAS#
(3)-(5)	idle
(6)	raise RAS#
(7)/(8)	idle

- CAS-before-RAS refresh (CBR)
(1) 	idle
(2)	lower CAS#
(3)	idle
(4)	lower RAS#
(5)-(7)	idle
(8) 	raise RAS#/CAS#

- hidden refresh
wouldn't fit in the scheme; instead of raising RAS# and CAS# in (8), only
RAS# will be raised and after a short period of time (RAS# precharge
time), RAS# is lowered again which activates a CBR cycle.

So if your RAMs support CBR-type refresh (i.e. they have their very own
refresh row counter), you want to go for that. If they don't, you need to
maintain your very own row counter (which must match the size of a row)
and apply the row address by your own.

> I know there are memory controllers that do all the job but if I
> could do with simple gates/inverters that's would be great,
> where I live trying to buy a digital IC other than 4000s are
> impossible !  (hope I'm no asking for so much)

I make that TTL since I'm not that familiar with the 4000s, just translate
the numbers to the respective couterparts.

Easiest way would be a 3-bit counter (e.g. 74191, just skip the 4th bit)
driving a 74138. That way you get low-active select signal for each stage.
However, you'd need hell of buffers for transferring row/col addresses and
buffer data. Probably the easiest would go for either a ready-made DRAM
controller, get into PICs or AVRs, or dig into PLD design.

Rainer