[sdiy] Finer points of sequencers
ASSI
Stromeko at compuserve.de
Sat Apr 12 11:39:37 CEST 2003
On Saturday 12 April 2003 09:19, Tim Ressel wrote:
> I have a few esoteric questions about sequencer
> design. The first is perhaps too esoteric. Picture a
> standard arrangement of a 4017 driving several pots
> which are then summed into an opamp. The 4017 outputs
> are actually cmos fets switching the output pin to
> either ground or +V. Now these fets have a non-zero
> resistance, and if you work out the thevenin
> equivelent you can see the finite resitance affects
> the output. Now since the off outputs are still in
> circuit, they are taking a little current from the
> summing node of the opamp.
Use an inverting summing opamp and this problem goes away, as you now
switch each signal onto the virtual ground and thus are all decoupled
from one another. You still have to deal with the finite conductance of
the output at the high side, so you have to provide a series resistance
before the pots. Of course you may also want to invert the signal again
(you probably will want to put some gain here, which needs to be
factored into the dimensioning of the summing stage).
> The second question is a bit more mainstream. When a
> sequencer is reset, it goes to the first output
> channel, yes?
In your circuit.
> The first clock pulse makes the second
> output active, yes? But is you are clocking off of a
> midi channel, isn't the sequencer now out of step with
> the midi clock?
Depends on your definition of sync. MIDI clock as such does not provide
a notion of steps, so it's up to you to define that relation.
> It seems like the first clock pulse
> after reset should give a gate output only, since the
> sequencer is already on the first output. Not that
> would be easy to rig.
Feed the reset for the 4017 through a FF that holds it until after the
next clock (coming from a mechanical switch it should be de-bounced
anyway). This way the 4017 ignores the first clock after reset, which
is what you likely want to happen. Another solution would be to hold
the reset up and dispatch it with the next clock, which might be easier
depending on how you are planning to produce the trigger and gate
signals.
Achim.
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