[sdiy] Finer points of sequencers

[Tim Ressel]

Hi all,

I have a few esoteric questions about sequencer
design. The first is perhaps too esoteric. Picture a
standard arrangement of a 4017 driving several pots
which are then summed into an opamp. The 4017 outputs
are actually cmos fets switching the output pin to
either ground or +V. Now these fets have a non-zero
resistance, and if you work out the thevenin
equivelent you can see the finite resitance affects
the output. Now since the off outputs are still in
circuit, they are taking a little current from the
summing node of the opamp. It seems to me that if the
fet resistances are not equal, then changing one pot
could slightly affect the tuning of other pots. Has
anyone seen this? Or am I being way too picky??

The second question is a bit more mainstream. When a
sequencer is reset, it goes to the first output
channel, yes?. The first clock pulse makes the second
output active, yes? But is you are clocking off of a
midi channel, isn't the sequencer now out of step with
the midi clock? It seems like the first clock pulse
after reset should give a gate output only, since the
sequencer is already on the first output. Not that
would be easy to rig. I thought about having the
sequencer go to the last stage on reset, but that gets
sticky on adjustable-length sequencers.

Help??

--Tim

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