[sdiy] uC with mul

[Magnus Danielson]

From: Jim Patchell <patchell at silcom.com>
Subject: Re: [sdiy] uC with mul
Date: Fri, 04 Jan 2002 12:47:22 -0800

Jim, Paul,

> Paul Maddox wrote:
> 
> > Jim/Harry,
> > 
> > I have some VHDL code written by a friend and some of it makes sense, and
> > some of it just looks like russian to me..
> 
>    VHDL is sort of based on ADA....the MIL SPEC computer language (a mil 
> spec mouse is an elephant!).  I have only done one VHDL design, and, I 
> have to admit, VHDL is very powerful, but man, you sure to have to type 
> in so much crap just to do a simple little function.

VHDL is indeed powerfull, but also more formal than Verilog. If you
learn the modeling ideas behind VHDL and learn to design good designs
(using generics and possibly also generate) you can do alot.

I have only VHDL experience and no Verilog experience, so I shall not
try to compare them too much, but I think there is indeed a point in
how VHDL works where as Verilog has some benefits on certain details.
In the end I prefer to use VHDL since I really like its inner working.
With the VITAL stuff (especially the more recent developements) and
SDF annotations I think it comes up to par with Verilog while being
better at formalism and models.

Cheers,
Magnus