[sdiy] CMOS schmitt trigger question

[harry]

media at mail1.nai.net wrote:

> First off, thanks to everyone who answered my question!!
>
> >Parallel connected gates offer only one advantage : drive strength.
> >If you parallel up 2 inverters, you can source and sink twice as much
> >>current.
> >
> >This technique is usually used to drive heavy or capacitive loads (low
> >resistance, or long wire leads... fr'instance.
>
> So if they are connected in parallel going to a CMOS input (which draws
> almost no current) is it a bad design, or they are merely trying to tie up
> unused gates??

Does not mean a bad design... could be a convenient tie point... or trying to
charge the CMOS input capacitance faster... probably not too significant at
maybe 5 - 15pF...

> I thought only the inputs needed to be terminated.

That's right. Don't tie the outputs...

> >Don't do this with different packages... the matching
> >is not good enough.
>
> Thanks for the tip.
>
> >I have usually not seen this done with the schmitt
> >trigger type gates. I don't know if the gate to gate
> >matching is as good ???
>
> I have no idea, but what really confuses me here, is that I thought CMOS
> outputs source current when high, and sink current when low, but according
> the notes, the output current is listed as a negative value when high, and
> positive value when low.  So I think I must be missing something very
> important!!

Maybe conventional current flow vs hole flow. Do you like current to flow from
positive to negative... or negative to positive ?   Makes no difference either
way in this case.  I usually say current is being sourced if the load is being
driven from
the psotitive rail... and sunk if it is being sucked down to the negative rail.

Gene Zumchak used the convention "sucked" and "blown" in his OTA Tutorial
(at Rene Schmitz's web site)  I like this because there is no confusion.  The
industry
I work in has a lot of trouble with this point... no one is sure what they are
talking about.  I have not got them to agree to "sucked and blown" as a
definitve terminology.  ;^)

> >Used in series, there are a couple of reasons they are used:
> >
> >As a buffer, to clean up a signal without inverting it.
>
> That makes perfect sense, the hysteresis would prevent an ambivalent signal
> from chattering.
>
> >As a fixed delay... all gates have a certain amount of propagation delay.
> >>You can use multiple gates in series to introduce a fixed delay
> >>(propagation delay * #of gates) Usually in the low mS range.
>
> According to the application notes, each gate has a transition time and
> propagation delay adding up to a few hundred nanoseconds, so you meant to
> say "uS", right??

Let the author 'fess to that one...

H^) harry


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