[sdiy] CMOS schmitt trigger question

[media at mail1.nai.net]

First off, thanks to everyone who answered my question!!

>Parallel connected gates offer only one advantage : drive strength.
>If you parallel up 2 inverters, you can source and sink twice as much
>>current.
>
>This technique is usually used to drive heavy or capacitive loads (low
>resistance, or long wire leads... fr'instance.

So if they are connected in parallel going to a CMOS input (which draws
almost no current) is it a bad design, or they are merely trying to tie up
unused gates??  I thought only the inputs needed to be terminated.

>Don't do this with different packages... the matching
>is not good enough.

Thanks for the tip.

>I have usually not seen this done with the schmitt
>trigger type gates. I don't know if the gate to gate
>matching is as good ???

I have no idea, but what really confuses me here, is that I thought CMOS
outputs source current when high, and sink current when low, but according
the notes, the output current is listed as a negative value when high, and
positive value when low.  So I think I must be missing something very
important!!

>Used in series, there are a couple of reasons they are used:
>
>As a buffer, to clean up a signal without inverting it.

That makes perfect sense, the hysteresis would prevent an ambivalent signal
from chattering.

>As a fixed delay... all gates have a certain amount of propagation delay.
>>You can use multiple gates in series to introduce a fixed delay
>>(propagation delay * #of gates) Usually in the low mS range.

According to the application notes, each gate has a transition time and
propagation delay adding up to a few hundred nanoseconds, so you meant to
say "uS", right??