At 8:48 PM -0600 2002/02/13, J. Larry Hendry wrote:
>Here is the idea: Feed the gate signal into the VC lag. Set the down lag
>time for zero. Take the output and run to 3 comparators. Each comparator is
>set to turn on its output at a progressively higher level. The output of
>each comparator is used as the delayed gate. So, now I have 4 gate signals
>turning on a 4 different times - the original gate, and the 3 comparator
>outputs. The up lag time sets the overall delay range. The comparator set
>points set the relationship between gate times. Since the 820 is set for lag
>only in the up position, all gates would end at the same time.
You can sort of do this will a few 700s. Plug the 820 outs to the 700
CV ins. Plug a DC bias into the IO A/C inputs. Plug nothing into IO
B/D inputs. Set the thresholds to different values to get delayed
gate outputs.
>The more I think about comparators, the more useful I see these generic and
>apparently useful utility circuits. I guess I am surprised that more people
>on the list have not talked about them.
I'd like to see some kind of comparator functionality in a future
module. With thresholds for both the up side and the down side (sort
of like adjustable hysteresis). These thresholds would be voltage
controllable, of course.