I created a group specifically to talk about this, so it won't get lost in the rather prodigious shuffle here.
http://tech.groups.yahoo.com/group/Inkjet_PCB_Construction/Steve Greenfield AE7HD
--- In Homebrew_PCBs@yahoogroups.com, brane2 <brankob@...> wrote:
>
> @Volkan Sahin:
>
> Thanks for your response. If by some "IP problems" you mean problems
> with Verilog/VHDL source for FPGA, I don't care too much about that.
>
> I hope you haven't been bullied by Epson about protocol technicalities
> and so you can clarify things there.
>
> As things were presented, it looks as each piezo has two parts:
>
> - one common to all piezos that is driven by a waveform on COM signal
> that does actual pumping the ink either in or out
>
> - per-nozzle signals that modulate common stream for each nozzle.
> Nozzles are driven serially through C/M/Y/K channel, two bits per nozzle.
>
> Start of the bits packet is signalled by "latch enable" and nozzles are
> fired simoultaneously with NCHG.
>
> Is this about right ?
>
> As I understand your data, COM waveform has to be shifted in somehow,
> and and you need 32 bits for that. Missing part is how and what exactly
> do they mean.
> Looking at waveform, it seems that each waveform has less than 8
> segments and if each one is described by 4 bits, probably 2 are for
> length and 2 are for direction.
>
> But looking at the scheme it seems signal is driven by the hardware
> itself ( your board has push-pull for it), so it is unclear why and how
> would one have to shift its digital representation to the chip and why.
>
> Could you go over that part ( signal generation and their purpose ) more
> thoroughly ?
>