On Sat, Feb 19, 2011 at 6:22 PM, designer_craig <
cs6061@...> wrote:
>
>
> Yes, if you connect a new component pin up to a existing net becomes part
> of the net. There is an exception in the PCB layout program. It is sometimes
> possible to run some copper tracts that would allow you to short two
> different nets. This can happen in a hand rout situation but the post layout
> design rule checks should flag this.
>
> Sometimes its desirable to connect two nets together, like for example a
> signal ground net connecting to a chassis ground net. You have component
> pins on each net but want them connected together only at one point on the
> layout for signal integrity reasons. So some packages have a virtual
> component you place on the schematic, it has two pins one connected to each
> net. No actual component is put on the board it just allows you to connect
> the two nets without the DRC's complaining that you have shorted the nets.
>
Heh, and if you're a ∗HDL designer / ASIC person, you got to watch out for
those pesky "wire patches" that connect 2 nets together - no component gets
placed in the design either, and they lead to all kinds of interesting fun
if you skip some automated check steps (because the tech kit doesn't work
properly with the verification tools, and there's no time to fix it before
the deadline), like completely dead ASICs - OOPS! The project I'm working on
has had at least 3 completely DOA ASIC runs, due to issues around connecting
different nets together! Good thing it's just grad school - in the real
world, I'm sure people would've been fired! Probably especially in the 2
cases where VDD got inadvertantly connected to GND - yay, we built a $5000
heater!
Andrew
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