Yes, if you connect a new component pin up to a existing net becomes part of the net. There is an exception in the PCB layout program. It is sometimes possible to run some copper tracts that would allow you to short two different nets. This can happen in a hand rout situation but the post layout design rule checks should flag this.
Sometimes its desirable to connect two nets together, like for example a signal ground net connecting to a chassis ground net. You have component pins on each net but want them connected together only at one point on the layout for signal integrity reasons. So some packages have a virtual component you place on the schematic, it has two pins one connected to each net. No actual component is put on the board it just allows you to connect the two nets without the DRC's complaining that you have shorted the nets.
Craig
--- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@...> wrote:
>
> Awesome thanks ..
> So if a pin on an IC for example, goes to a cap, and a resistor .. then that
> would be one net thats
> attached to 3 places .. and might show up as IC1.1, C1.1 and R1.1 something
> like that .. and
> the only way something else could become a part of that net name or number would
> be if it was
> connected directly to the traces going to one of those points ?? Is that correct
> ?
>
> Randy
>
>
>
>
> ________________________________
> From: designer_craig <cs6061@...>
> To: Homebrew_PCBs@yahoogroups.com
> Sent: Sat, February 19, 2011 4:44:11 AM
> Subject: [Homebrew_PCBs] Re: NETS
>
>
>
> Randy,
>
> In any electronic circuit, the pins of the various components that are
> connected together are called a net. Generally a net connects two or
> more component pins and a circuit or schematic design is a collection of
> one or more nets. A schematic is just a graphical way of representing
> what component pins must be connected together for the design. The
> schematic capture program (editor) will assign a net name to each of the
> unique nets in the design. Most programs assign the nets a numeric name
> but usually allow the user to change this to something more useful like
> "reset" or "clock" etc. Debugging a design is much
> easier if all the nets have some functional name. Most of the schematic
> capture packages that I have used allow you to draw a stub of a wire to
> a component pin and assign it a net name. All stubs that have the same
> name are on the same net and connected even though there is no direct
> graphics line on the schematic. This is a "connect by name"
> feature and is quite useful in complex designs. Things get a little
> more complex when you have busses, which are sort of a short hand for a
> collection of similar named nets or have a hierarchical schematic. In
> high-end programs nets can be assigned various properties in addition to
> just a name and are used to guide the PCB layout process. Things like
> the maximum number of vias, trace width, trace spacing, layer and
> propagation delay are common. With today's high-speed processors
> and memory impedance control and trace propagation delay matching are
> critical to proper operation. Once the design is in the PCB layout
> stage these net properties can be used to guide both manual and
> auto-routing of the board, they are also used for post layout design
> rule checking.
>
> Once in the PCB layout program each net becomes a copper tract (or
> plane) that connects the component pins assigned to that net.
>
> Most schematic packages will let you output a "net list" which is
> usually a text file containing a list of nets in the design and the
> component pins asigned. ie. ( clock: U1-4 U8-5 ) And most PCB
> layout packages will accept a text file net list as input.
>
> In additon to a list of NET's the PCB layout software needs to know what
> footprint to use for a particular component. Generally, but not always,
> the footprint name is attached as a property to the component symbol
> used when drawing the schematic and provided to the PCB program when the
> PCB program reads in the schematic.
>
> Craig
>
> --- In Homebrew_PCBs@yahoogroups.com, "Randy S." <rj3819@> wrote:
> >
> > Whats the concept of "nets" in all this pcb creation process?
> >
> > Randy
> >
>
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