--- In
Homebrew_PCBs@yahoogroups.com, "derekhawkins" <eldata@...> wrote:
>
> >I don't think that works for SMT parts, Alan.
>
> Eagle would be crap if it didn't. I use that feature often;
>
> One layer;
> http://www.pbase.com/eldata/image/57091286/large
>
> The other;
> http://www.pbase.com/eldata/image/57091263/large
Yes, Derek, I'm glad you showed me how to group parts together to move
en masse. I am glad because I didn't have to read the HELP !
Anyway, regarding the polygon fill technique discussed earlier:
I noticed when filling polygons ∗∗after∗∗ I had routed traces, the
polygons appeared to be electrically isolated from the bottom layer
traces, even using the same layer color. No matter how close I put
the polygon vertices to the component leads, a thin black line
separated the polygon from the traces after redrawing. I think this
means the polygons were electrically isolated from the traces. I'm
not sure. There must be some way to merge the solid polygons and
vias in the same layer into one monolithic two-dimensional copper
pour. Any ideas? (ERC indicated 4 warnings, no errors.)