<div dir="ltr">This has been a lively topic. Here's a plot of the "bit reversed pwm":<div><br><div><img src="cid:ii_lq1scqwd0" alt="image.png" width="562" height="559"><br></div><div><img src="cid:ii_lq1scxbr1" alt="image.png" width="562" height="154"><br></div><div><br></div><div><br></div><div>and python snippet to update the .ipynb:</div><div><font face="monospace">def mwp(bitdepth, copies):<br> """bit reversed pwm"""<br> a = np.zeros((pow(2,bitdepth)+1, pow(2,bitdepth)*copies), dtype=np.uint)<br> maxval = pow(2,bitdepth)<br> for i in range(0,maxval+1):<br> for t in range(0,a.shape[1]):<br> acc = t%(maxval)<br> b = '{:0{w}b}'.format(acc, w=bitdepth)<br> rev = int(b[::-1], 2)<br> a[i,t] = rev < i<br> return a <br></font></div><div><font face="monospace">plt.figure(figsize=(16,16))<br>plt.imshow(mwp(8, 1), cmap='binary', origin='lower')<br>plt.figure(figsize=(16,4))<br>plt.imshow(mwp(8, 4), cmap='binary', origin='lower')</font><br></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Dec 11, 2023 at 7:05 PM brianw <<a href="mailto:brianw@audiobanshee.com">brianw@audiobanshee.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
<br>
On Dec 11, 2023, at 9:04 AM, Vladimir Pantelic wrote:<br>
> On 12/11/23 17:00, Mike Bryant wrote:<br>
>> Using SPI requires continuous mode which I'm not sure most STM32s support.<br>
> <br>
> should be no isssue when doing circular DMA (and the source memory can keep up)<br>
<br>
The limitation is not pulling data from memory via DMA, but placing that data on the SPI bus given a clock rate. 16-bit data takes at least 16 clocks for the data, plus maybe another clock for a gap between words, depending upon how the two sides (CPU and external device) are designed.<br>
<br>
I believe that Mike is using the phrase, continuous mode, to refer to SPI transfers that do not lose a clock cycle between words. i.e. Every clock cycle has data, with no gap, and thus continuous data.<br>
<br>
<br>
Beyond merely the various interpretations of SPI for general communications, there's also the serial digital audio bit stream busses that are common. Those tend to have a clock signal, a data bit, a word sync bit, and sometimes a channel sync bit. For digital audio CODECs, every clock is accompanied by a new data bit. The word sync keeps each audio sample separate, usually by asserting at or before the first bit of each new word. The channel sync bit is used for stereo and other multichannel streams, and is asserted for the first channel in the sequence, usually left for stereo, or Channel 0 for multichannel. I think there's never a gap for dedicated digital audio streams.<br>
<br>
Regular SPI protocols that aren't specifically for audio usually don't have the extra bits for synchronizing words and thus they have to use some other technique to know which bits belong together in a sample value. Sometimes that's done by flipping the Chip Select between each word, sometimes it's with a gap in the data, or the devices simply count clocks and thus will get way out of sync if a single clock is missed.<br>
<br>
Brian<br>
<br>
<br>
________________________________________________________<br>
This is the Synth-diy mailing list<br>
Submit email to: <a href="mailto:Synth-diy@synth-diy.org" target="_blank">Synth-diy@synth-diy.org</a><br>
View archive at: <a href="https://synth-diy.org/pipermail/synth-diy/" rel="noreferrer" target="_blank">https://synth-diy.org/pipermail/synth-diy/</a><br>
Check your settings at: <a href="https://synth-diy.org/mailman/listinfo/synth-diy" rel="noreferrer" target="_blank">https://synth-diy.org/mailman/listinfo/synth-diy</a><br>
Selling or trading? Use <a href="mailto:marketplace@synth-diy.org" target="_blank">marketplace@synth-diy.org</a><br>
</blockquote></div>