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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Given the price of MN3205s, I suspect an A-D, processor for delay and then D-A would work out cheaper, give longer delays and give less noise.<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Synth-diy [mailto:synth-diy-bounces@synth-diy.org]
<b>On Behalf Of </b>Didier Leplae via Synth-diy<br>
<b>Sent:</b> 16 June 2022 06:28<br>
<b>To:</b> Michael E Caloroso<br>
<b>Cc:</b> Synth-diy Mailing List<br>
<b>Subject:</b> Re: [sdiy] Using dual BBD chips for higher clock frequency<o:p></o:p></span></p>
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<p class="MsoNormal">Yes, we are using a compander as well. I forgot to mention that. I guess what you’re saying is that each chip introduces a certain amount of noise, so using two chips makes it worse. That’s interesting <o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">On Jun 16, 2022, at 12:23 AM, Michael E Caloroso <<a href="mailto:mec.forumreader@gmail.com">mec.forumreader@gmail.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">Chaining BBD devices increases the noise. I recommend using a compander in your design.<o:p></o:p></p>
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<p class="MsoNormal">MC<o:p></o:p></p>
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<p class="MsoNormal">On Wed, Jun 15, 2022 at 7:38 PM Didier Leplae via Synth-diy <<a href="mailto:synth-diy@synth-diy.org">synth-diy@synth-diy.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">Oops, I see I mis-numbered my questions. Here is the message with questions properly numbered <img border="0" width="16" height="16" id="_x0000_i1025" src="https://s.yimg.com/nq/yemoji_assets/latest/yemoji_assets/1f605.png" alt="Emoji">:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">I'm currently working on a bucket brigade delay module using the MN3205 chip. The circuit is based on the Jan Hall article in Electronotes 87 (except using MN3205). I'm
interested in trying to add a second MN3205 chip in series in order to double the clock frequency thus reducing clock noise issues. Has anyone had experience doing this?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">Here are a few questions I have:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">1) Do I need to put any sort of buffering between Chip#1 & Chip#2?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">2) Do I need a biasing trim pot before each chip? Or just Chip#1?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">3) Do I need to connect both outputs of Chip#1 through a clock null trim into Chip#2?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif"">4) I'm using a PIC chip to generate the clocks. Would I need to put any sort of buffering to isolate the clock inputs of the two chips?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Verdana","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">On Wednesday, June 15, 2022, 06:27:51 PM CDT, Mike Bryant <<a href="mailto:mbryant@futurehorizons.com" target="_blank">mbryant@futurehorizons.com</a>> wrote:
<o:p></o:p></span></p>
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<p><span style="font-size:11.0pt;font-family:"Helvetica","sans-serif";color:#1F497D">I’ve never used that device, but on your last point it does have a lot of capacitive load so may be best to use a buffer to isolate the PIC from the load, in which case use
a dual buffer anyway.</span><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"><o:p></o:p></span></p>
<p><span style="font-size:11.0pt;font-family:"Helvetica","sans-serif";color:#1F497D"> </span><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"><o:p></o:p></span></p>
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<p><span style="font-size:11.0pt;font-family:"Helvetica","sans-serif";color:#1F497D"> </span><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"><o:p></o:p></span></p>
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<p><b><span lang="EN-US" style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">From:</span></b><span lang="EN-US" style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> Synth-diy [mailto:<a href="mailto:synth-diy-bounces@synth-diy.org" target="_blank">synth-diy-bounces@synth-diy.org</a>]
<b>On Behalf Of </b>Didier Leplae via Synth-diy<br>
<b>Sent:</b> 16 June 2022 00:17<br>
<b>To:</b> Synth-diy Mailing List<br>
<b>Subject:</b> [sdiy] Using dual BBD chips for higher clock frequency</span><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"><o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">I'm currently working on a bucket brigade delay module using the MN3205 chip. The circuit is based on the Jan Hall article in Electronotes 87 (except using MN3205). I'm interested
in trying to add a second MN3205 chip in series in order to double the clock frequency thus reducing clock noise issues. Has anyone had experience doing this?<o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">Here are a few questions I have:<o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">1) Do I need to put any sort of buffering between Chip#1 & Chip#2?<o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">2) Do I need a biasing trim pot before each chip? Or just Chip#1?<o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">3) Do I need to connect both outputs of Chip#1 through a clock null trim into Chip#2?<o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A"> <o:p></o:p></span></p>
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<p><span style="font-size:10.0pt;font-family:"Helvetica","sans-serif";color:#26282A">2) I'm using a PIC chip to generate the clocks. Would I need to put any sort of buffering to isolate the clock inputs of the two chips?<o:p></o:p></span></p>
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