<html><head><style> body {height: 100%; color:#000000; font-size:12pt; font-family:times new roman,new york,times,serif;}</style></head><body><div>Although this sort of defies conventional wisdom, I've often fixed CD4024 (and other 4000 series clocked circuits) with a small capacitor from the clock</div><div>input to ground. I suspect I had some noise or glitch around the trigger point and this damped out the anomaly.</div><div><br></div><div>It might double clock, or triple clock etc. on a noise at the transition point.</div><div><br></div><div>We are talking maybe 15 - 50pf or so...</div><div><br></div><div>Another issue is counters that have "schmitt trigger" on the inputs. One manufacturer used a schmitt trigger as the input stage (right) and another who cloned the chip used an ordinary logic buffer ~followed~ by a schmitt trigger as the second stage. So it the first gate screws up and multi-clocks the schmitt trigger makes the rise time of the defective clocks even faster (what were they thinking?). Today there might only BE one manufacturer... To bad 4000 series was one of my favorite families of all time. But with sub 5V supplies it's no longer good...</div><div><br></div><div>Harry</div><div><br></div><div>----- Original Message -----<br>From: David G Dixon via Synth-diy <synth-diy@synth-diy.org><br>To: synth-diy@synth-diy.org<br>Sent: Mon, 20 Sep 2021 21:18:58 -0400 (EDT)<br>Subject: Re: [sdiy] Issue with CD4024 Ripple Counter<br></div><div><br></div><div><br></div><div><span class="684555200-21092021">Just for Ss and Gs, I thought I'd show you <br>my layout graphic for the ASR board which has the clock circuit on it. <br>Please see attached. Note that red traces are the +V rail <br>and green traces are the GND rail (and black traces are the -V <br>rail). The CLOCK pin of the 4024 is connected to the light blue <br>trace. I've also attached what I call the "Build" picture, which is what <br>the board actually looks like. Finally, I've attached a picture of the <br>actual board. Note that there is another circuit board that this one plugs <br>into, which has a DG333 and comparators for controlling the "Shift/Bypass" <br>switches on each ASR channel electronically. That's what the 3- and 4- pin <br>headers plug into. The 4-pin header passes through that board and connects <br>to the Panel PCB. This is where the clock signal comes in and out of this <br>board.</span></div><div><span class="684555200-21092021"></span> </div><div><span class="684555200-21092021">The rail traces are a bit thicker than the <br>other traces. You will notice that the ground traces do not connect to <br>each other across the top of the board, so that the ground at the 4024 actually <br>comes up from the bottom. I just tried jumpering the two ground traces <br>temporarily with alligator clips and it had no effect (and why should <br>it?).</span></div><div><span class="684555200-21092021"></span> </div><div><span class="684555200-21092021">Also, I should mention that when the ASR is <br>being clocked by an external LFO, the CD4024BE is clocking on the positive edge <br>only. However, when the Manual clocking switch is used, the CD4024BE is <br>clocking on both edges. The clock signal at the CLOCK pin looks identical <br>in either case. The manual clocking switch is connected to the +V and GND <br>rails, and is fed to the comparator through a 1k resistor, whereas the clock <br>input jack is connected through a 10k resistor. Why any of this should <br>have an effect is beyond me. This, for me, is now more or less in the <br>realm of the supernatural, in terms of my ability to understand <br>it.</span></div><div><br></div><div><br></div></body></html>