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</o:shapelayout></xml><![endif]--></head><body lang=FR-CA link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span lang=EN-CA style='color:#1F497D'>Sorry, please forget the previous email..<br>The following circuit is what should be (D1,D2 displaced):</span><span lang=EN-CA><o:p></o:p></span></p><p class=MsoNormal><span lang=EN-CA style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='color:#1F497D;mso-fareast-language:FR-CA'><img width=846 height=657 id="Image_x0020_1" src="cid:image002.jpg@01D70395.4C178820"></span><span lang=EN-CA style='color:#1F497D'><br><br><o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='mso-fareast-language:FR-CA'>Here is a revised version of the ADC/DAC circuits according (I think)<br>to what has been suggested and pointed out such as:<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='mso-fareast-language:FR-CA'>ADC’s Input bias current vs driving opamp’s output impedance<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='mso-fareast-language:FR-CA'>Resulting in pour linearity of incoming CVs,<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='mso-fareast-language:FR-CA'>LPF bad results on ADC readings (R1 and former C1 removed cap ).<br>BTW, +5v reference will be from a REF02 0.2% precision<br>and as shown will drive both ADC/DAC.<br>OP275 seems to be a good choice for driving the ADC<br>but I hope more buffering 2 chained opamps won’t bring too much offset voltage<br>to AIN input here..<o:p></o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='color:black'><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='color:black'><o:p> </o:p></span></p><p class=MsoPlainText><span lang=EN-CA style='color:black'><o:p> </o:p></span></p></div></body></html>