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<p>DPW?<br>
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<div class="moz-cite-prefix">On 8/6/2018 6:20 PM, Andrew Simper
wrote:<br>
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cite="mid:CAAxOnzZd3u9E7kDHQO+88D0vcuC-dxs12xXYV+hvLEU8ffVO8g@mail.gmail.com">
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<div dir="ltr">And don't forget DPW as an easy to implement method
to reduce aliasing. You can use an interpolated inverse table
and the error only appears as slight differences in amplitude,
it doesn't reduce the efficacy of the anti-aliasing (which is
the case with BLEP if you don't have a good division). As long
as you can easily generate the intergrated waveshape equation
and compute that efficiently you can do DPW efficiently and it
will tilt the spectrum by -6 dB/Oct, which will reduce the
oversampling overhead considerably.</div>
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<div dir="ltr">On Mon, 6 Aug 2018 at 08:49, <<a
href="mailto:rsdio@audiobanshee.com" moz-do-not-send="true">rsdio@audiobanshee.com</a>>
wrote:<br>
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<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex">If you’re
willing to consider building everything on an FPGA, then I
suggest that you should definitely consider a DSP. You’ll get
more bang for your buck with a DSP - unless you literally pay
for an FPGA that has full DSP slices in it - and it will be
easier to work in an instruction set that has been optimized
for decades for exactly the kind of thing you’re doing.<br>
<br>
Top contenders would be the TMS320, especially the C5000 or
C6000 series, and the SHARC.<br>
<br>
I addition to the math support and large accumulators, you’ll
also get timer peripherals and serial ports that support
digital audio connections to multi-channel DACs.<br>
<br>
I’ve done some complex designs, and using a DSP is basically
as flexible as an FPGA without the overhead of creating or
finding and adapting the various IP blocks. You’ll also have
the benefit that there won’t be as much wasted power.<br>
<br>
Brian<br>
<br>
<br>
On Aug 3, 2018, at 8:50 PM, Tim Ressel <<a
href="mailto:timr@circuitabbey.com" target="_blank"
moz-do-not-send="true">timr@circuitabbey.com</a>> wrote:<br>
> I have a design for a complex VCO that will include 9
NCOs. While the polyBlep stuff looks interesting, I am
wondering if I can pull it off with an FPGA. So the 9 NCOs
would run at a high rate, say 2MHz. Then they get mixed,
filtered, and downsampled to about 50KHz. The filter is the
part I am not sure of, but its been done before so it is just
a matter of working it out.<br>
> <br>
> I figure by the time I get a processor powerful enough to
do this, and FPGA is cheaper maybe?<br>
> <br>
> Am I more out of my mind than usual?<br>
> <br>
> -- <br>
> --Tim Ressel<br>
<br>
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<br>
<pre class="moz-signature" cols="72">--
--Tim Ressel
Circuit Abbey
<a class="moz-txt-link-abbreviated" href="mailto:timr@circuitabbey.com">timr@circuitabbey.com</a></pre>
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