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<div style="font-size: 10pt; "><p dir="ltr" style="margin-top:0;margin-bottom:0;">Checked my board stash, and there are a few boards which do have the outline, and a few that don't. It seems the tl072 component doesn't have the outlines, but a board with some smt tl074's and cmos does have outlines. (and I use lbr's that eagle came with)</p><p dir="ltr" style="margin-top:0;margin-bottom:0;">You could change the settings of the gerber cam to also include tdocu, that would be a quick fix.</p><p dir="ltr" style="margin-top:0;margin-bottom:0;">Best regards,</p><p dir="ltr" style="margin-top:0;margin-bottom:0;">Jarno.</p></div><div style="font-size: 10pt; "><div id="LGEmailHeader" dir="ltr" style="margin-top:0;margin-bottom:0;"><p dir="ltr" style="margin-top:0;margin-bottom:0;"><br></p><p dir="ltr" style="margin-top:0;margin-bottom:0;">------ Origineel bericht------</p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><b>Van: </b>Richie Burnett<rburnett@richieburnett.co.uk></rburnett@richieburnett.co.uk></p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><b>Datum: </b>vr, 20 nov. 2015 21:18</p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><b>Naar: </b>synth-diy;</p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><b>CC: </b></p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><b>Onderwerp:</b>[sdiy] Eagle footprints</p><p dir="ltr" style="margin-top:0;margin-bottom:0;"><br></p></div><pre>A question for the Cadsoft Eagle gurus...Just finishing off a PCB here with Eagle and noticed that all of the SOIC devices have no component outlines or orientation markings on the silkscreen layer, only tDocu which can be printed off as documentation to aid in assembly but doesn't end up in the silkscreen Gerber file. All other semi packages used on this board like TSSOP, TQFP, SOT23 etc, have at least partial outlines and orientation markings on the silkscreen layer, often with more extensive detail on the tDocu layer. I'm happy with <a href="http://these.Is">these.Is</a> there some reason for this? Did Cadsoft just forget to put orientation markings in the SOIC package footprints in their libraries, or is there some rule of PCB design somewhere that says there shouldn't be silkscreen ink under SOIC devices? Does it interfere with the correct seating of SOIC packages during reflow, or can I just add silkscreen orientation marks under the device body to the footprints that I'm using to aid? I can understand not putting silkscreen orientation marks under QFNs that are planar on the bottom and pretty much have to be put on by machine anyway, but some orientation marks on SOIC's would really help with manual placement.I realise that any marking underneath the ICs will be covered after fitting and make checking device orientation difficult, but I'd rather not put orientation marks outside the perimeter of the part as component packing density is very high!I'm interested to hear any thoughts on this,-Richie, _______________________________________________Synth-diy mailing<a href="mailto: listSynth-diy@dropmix.xs4all.nlhttp"> listSynth-diy@dropmix.xs4all.nlhttp</a>://<a href="http://dropmix.xs4all.nl/mailman/listinfo/synth-diy">dropmix.xs4all.nl/mailman/listinfo/synth-diy</a></pre></div>
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