[sdiy] Roland's MB187123 / RD87123 Alpha Juno DCO chip

[Rainer Buchty]

On Mon, 24 Aug 2026, Tom Wiltshire wrote:

> What I don't have is any clue about the bus timing, but given there's 
> only 8 data lines and two control lines, how hard can it get?!

I'd say classic 8051 bus timing. After all, that's what it talks to and 
that's how the machine is set up.

A0-A7 are sampled with the falling edge of ALE, data then with the 
rising edge, timing like the standard 12MHz-clocked 8051 as in the 
datasheet, not the modern turbo variants.

> I suspect that the ALE (Address Latch Enable) line controls whether 
> data goes into the Address latch, or to whichever data latch (Wave or 
> Pitch) is selected by that address if not asserted.

Yep. ALE separates the function of AD0-7. While ALE=1, it's A0-7 
(sampled with falling ALE), while ALE=0, it's D0-7 (sampled with raising 
ALE).

Seeing that that the Gate Array controls DCO_CS#, but there's no RD#/WR# 
connection to the DCO, I think the DCO chip is write-only, so with CS#=0 
ALE=1 gives the internal register address, and ALE=0 the corresponding 
register data to be written.

Figuring them out will be the fun part. Probably 4-bit pre-divider 
(range), 16 bit frequency (maybe just 12 combined with the pre-divider), 
at least 8 bit pulse width, maybe more (the UI tells about 128 steps, 
but that'll get a crappy PWM, so internally there might also be an LSB), 
), some control word (PULSE and SAW modes, i.e. 2+3 bit. another 3 bit 
for the SUB mode -- makes 8 bit) and some more (sub and noise level, 
each 2 bits -- so maybe combined with the range divider, if the true 
frequency control is 16 bit, which I somewhat assume).

Probably in a block layout of 8 bytes, as 6-byte blocks would be hell of 
an internal addressing logic.

The 8032 disassembly should give a clearer picture here.

> There's other unknowns, like how many clock cycles it takes for the 
> data to be latched in.

I'd go for straight 8051 timing, that's how the system seems to tick 
according to the schematics.

> Plus the chip seems to include amplitude control features which aren't 
> shown in the diagram (controlled by the wave data latch, maybe?).

My gut feeling is that this probably just controls which output bit(s) 
the sub and noise outputs are ORed to before DAC'ing the output bit 
pattern.

> Finally, I'm sort-of curious about those two "TST" pins. Looks like 
> "Test" to me. but what does a test mode do on such a chip, and why 
> didn't Roland use it in the Alpha Juno? (both lines are tied 
> permanently low). Maybe that's not it.

If it is just chip-production testing, why would they use it? Might not 
be useful at all in the synth, like selecting SAW, SUB, and NOISE on all 
outputs.

If you don't fear breaking it, just feed it something else but (0,0) 
there and check with the scope on the output pins.

At least we can be sure that they are not RD# *and* WR#, otherwise (0,0) 
wouldn't work. But one could be RD/WR# to allow read-back of stored 
register values and internal states. As such, the other could be A8, 
separating between the user-accessible registers and the internal state 
registers (like per-voice phase accumulator and saw/pulse/sub/noise 
outputs).

Considering testing, this might even make more sense that the first 
scenario I described.

Cheers,
 	Rainer