[sdiy] Digital Waveshape Generator.

[Phillip Harbison]

Richie Burnett wrote:
> I think you might have made a mistake calculating your divider ratios... 

At least one. ;)

First, I got the master clock frequency wrong. It should be 14417920.
Not 1802240 (which is 1/8 of 14417920). Not sure when I divided by 8.

> You need to divide the master clock frequency down to a frequency that 
> is 256 times that of the note you want to produce, ...

Correct. I forgot about that. 256 * 14417920 is 3.69 GHz which is beyond 
even ECL. I think the 65-year-old me forgot what the 21-year-old me had 
determined after lots of pondering. I remember considering using a phase
locked loop to multiply the fundamental frequency, but I thought the 
time to lock after changing notes would take too long and be audible.

I could use my divider scheme and 14.4 MHz clock to generate the 12 
notes of the top octave and use PLLs to multiply each by 256, but 12 
PLLs and 12 sets of counters is a lot of chips. That all might fit in an 
FPGA. At least the individual voices could share the top octave clocks. 
Each voice could use a multiplexer to select one of the 12 clocks. I 
think I still need all those counters even though I would only need to 
divide by powers of 2 (e.g. to convert from 256 * A8 to 256 * A1).

I had ordered 4 PLL chips (Analog Devices ADF4153). Now I need 8 more!
This is getting less interesting by the minute. :(

Thanks for pointing out the errors.

-- 
Phil Harbison