[sdiy] Frequency shifted from BBD?

[Mike Bryant]

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Besides the point that Tom raises, there's another consideration: Using an MCU to program a complex digital signal is often more wasteful (think: battery-draining) than judicious use of logic gates.

Sorry but this usually isn't the case.  Unless you are switching at a very low rate, discrete logic gates have to drive the capacitances on the PCB between each other whereas MCUs do all the work internally and just output the final waveform.   10 cent OTP MCUs cost less than many logic gates due to higher volumes and usually use less power and PCB area so system cost is lower.
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From: Synth-diy <synth-diy-bounces at synth-diy.org> on behalf of brianw <brianw at audiobanshee.com>
Sent: 09 October 2024 05:14
To: SDIY <synth-diy at synth-diy.org>
Subject: Re: [sdiy] Frequency shifted from BBD?



On Oct 6, 2024, at 4:09 PM, Benjamin Tremblay wrote:
> Why not generate the clocks with the MCU and skip voltage control?

Besides the point that Tom raises, there's another consideration: Using an MCU to program a complex digital signal is often more wasteful (think: battery-draining) than judicious use of logic gates.

A counter can divide down a higher clock rate. A couple of AND gates plus an inverter can generate non-overlapping clock signals from the two LSB outputs of the counter. Gates like these are cheap in CMOS.

Doing the same with an MCU would be unwieldy unless you have hardware support. It might be possible to convince the timer/counter motor control peripheral of certain MCU chips to create non-overlapping clocks at identical rates.


> I just assumed Eventide used a digital pathway.

I'm sure Eventide did use a digital pathway, but it was almost surely built on a lot of discrete logic instead of pure software.


> As a teenager I got one of those Radio Shack kits to build the SAD1024 BBD delay.

I also built a DIY BBD delay. I fudged many of the potentiometer values to get longer delays - a much lower fidelity than a commercial product would allow. Super fun experimentation. Basically, I allowed the clock to be cranked much lower than the original schematic. I knew it would sound bad, but I wanted the flexibility. That box had very sensitive controls, because each pot spanned a much wider range than would be considered ergonomic design.


> Anyways… I have thought it would be fun to get a huge BBD with 4096+ stages and run it at a really high speed.
> If I understand, there’s a problem with speed; the sample/hold cells have slew rate caused by their capacitance, right?

The FET switches between each pair of cells have some "on" resistance, albeit small, so the RC circuit formed by the on resistance and the capacitor put a limit on the clock speed. You can clock faster, but the cells will not be fully charged. If the signal is low amplitude, then it might pass through, but a high amplitude signal would require big changes in the cell charge, and the voltages would not get through in full.

> It seems like a lot of work to get a mid-quality sound.

Don't forget the noise - you get a lot of noise, too.

> Benjamin


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