[sdiy] Critique my gate output buffer?

Paul Glass-Steel pfglasteel at gmail.com
Sun Nov 24 18:38:27 CET 2024


I'm hoping to improve on the typical transistor emitter-follower, wire-OR
capable gate output buffer that many of my modules have inherited from CGS
and NLC. I've come up with this: https://tinyurl.com/259pt83t - it seems
happy on my bench, the voltage is stable under a lot of fan-out to multiple
inputs and it seems ok with long cables / capacitive loads. But I thought
I'd check here to see if I'm missing something.

Thanks,
-Paul
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